Reduction in the sizes and the inherent features of semiconductor devices (e.g., a Metal-Oxide-Semiconductor (MOS) device) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades.
To enhance the performance of MOS device, stress may be introduced into the channel region of a MOS transistor to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an N-type Metal-Oxide-Semiconductor (NMOS) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a P-type Metal-Oxide-Semiconductor (PMOS) device in a source-to-drain direction.
In conventional methods for generating a stress in a channel region of a MOS device, a first semiconductor material is grown on a second semiconductor material through epitaxy. The first and the second semiconductor materials have different lattice constants. Hence, a stress is generated in both the first and the second semiconductor materials. A gate stack is formed over the first semiconductor material to form the MOS device. The first semiconductor material forms the channel of the MOS device, wherein the carrier mobility in the channel region is improved. Due to the lattice mismatch, however, defects also occur at the interface between the first and the second semiconductor material, which defects may include, for example, lattice misfit defects. This may result in a high leakage current.